1. Field of the Invention
The present invention relates to a system decoder for an optical disc reproducing apparatus, and in particular, to a system decoder for a high-speed data transmission and a method for controlling track buffering.
2. Description of the Related Art
After an optical disc technique for reading information recorded on a recording medium by using a laser beam was established about 20 years ago, an optical disc reproducing apparatus such as a laser disc (LD) player or a compact disc (CD) player has come into wide use. Recently, commercialization for an optical disc recording and reproducing apparatus has made rapid advancement. Further, with the development of a shortwave laser and recording/reproducing technique, the density of the optical disc becomes quite high.
On the other hand, a digital image compression technique also has been developed remarkably. In particular, an MPEG2 (Moving Picture Experts Group 2) technique reproduces an image having a quality similar to that of the existing video apparatus, at a data transfer rate of close to 10 Mbps. Further, with the development of an AC-3 audio compression technique for reproducing a multichannel audio signal, one can enjoy audio and multi-sound of high quality at home. It is therefore expected that a digital video (or versatile) disc (DVD), developed under such a technical background, and a DVD-R (DVD-Recordable) will be a function substitute for the existing CD-ROM (Compact Disc-Read Only Memory) as well as the conventional VTR (Video Tape Recorder). As a disc-type recording medium for a digital moving picture, the DVD can record the MPEG2 digital image of over 2 hours, and is suitable for a promising multimedia recording apparatus which can process audio and video signals of high quality.
FIG. 1 illustrates a schematic block diagram of a general DVD reproducing apparatus. In the drawing, as a disc motor 16 rotates at a regular speed to rotate an optical disc 10, an optical pickup 13 having a head 12 picks-up information from the optical disc 10 and converts it into analog RF (Radio Frequency) signal. The optical pickup 13 is driven by a sled pickup motor 14. The analog RF signal is reshaped into a data stream ESM. The data stream ESM from the optical pickup 13 is applied to a digital PLL (Phase Locked Loop) 20 and a system decoder 18. The system decoder 18 performs demodulation, error correction, and descrambling operations with respect to the data steam ESM received from the optical pickup 13. The digital PLL 20 including a phase comparing circuit, a voltage controlled oscillator (VCO), and a frequency divider, generates a first clock synchronized with a signal reproduced from the optical disc 10. A disc driving controller 22 controls a constant linear velocity of the rotation of the disc and other disc related operations, in consideration of frequency servo and phase servo, in accordance with a frame synchronous signal Sf supplied from a synchronous detector (not shown) of the system decoder 18.
A microcomputer 24 performs an overall control operation of the DVD reproducing apparatus according to a control program. For example, the microcomputer 24 generates a transmission control signal in response to a data transmission start signal from an audio/video decoder (hereinafter, referred to as A/V decoder for short) or a ROM decoder 32. A system clock generator 26, which is a crystal oscillator, generates a second clock, i.e., a system clock PLCK to the disc driving controller 22 and an error correction circuit (not shown). Further, the system decoder 18 is coupled to first and second memories 28 ad 30. The first memory 28 is an error correction memory, and is commonly a static RAM (Random Access Memory), and the second memory 30 is a track buffer memory, and is commonly a dynamic RAM. The ROM decoder 32, which is commonly formed in a host computer (e.g., a personal computer), operates according to a control command from the host computer, and transfers the data generated from the system decoder 18 to the host computer based on a specified interfacing technique. A demultiplexer 34 demultiplexes audio and video signals from the system decoder 18 to an AC3/MPEG audio decoder 42 and an MPEG2 video decoder 36, respectively. The video and audio signals are decoded respectively at the video decoder 36 and the audio decoder 42, and transferred to a monitor 40 and a speaker 46 via an NTSC (National Television System Committee) encoder 38 (or a PAL (Phase Alternation Line) encoder) and a digital-to-analog (D/A) converter 44, respectively. The system decoder 18 according to the prior art is illustrated in detail in FIG. 2.
Referring to FIG. 2, the data stream ESM picked up from the optical disc 10 by the head 12 is demodulated by an EFM (Eight-to-Fourteen Modulation) demodulator 100 into an original state, in which the EFM demodulator 100 includes a 32-bit shift register 102 and a 16-to-8 demodulator 104. A synchronous detector 106 detects the frame synchronous signal Sf from an output signal of the 32-bit shift register 102 and provides it to the digital PLL 20. Further, an output of the 16-to-8 demodulator 104 is written into the first memory 28 under the control of an ECC memory controller 108. Afterward, the demodulation data written in the first memory 28 is read out by block units and transferred to an error correction circuit (ECC) 110, under the control of the ECC memory controller 108. The data corrected at the error correction circuit 110 is transferred to a descrambler and error detector 112, under the control of the ECC memory controller 108. A descrambler of the descrambler and error detector 112 descrambles data scrambled during a data encoding process to restore it to the original state, and the error detector of the descrambler and error detector 112 detects an error of the descrambled data. Commonly, the descrambling and the error detection are performed by sector units, and the detected error information is stored into the second memory 30 together with main data MD under the control of a track buffer memory controller 120. The track buffer memory controller 120 generates an acknowledge signal according to a predetermined priority order, in response to a memory access request signal from a buffer write controller 114, a buffer read controller 118, and a microcomputer I/F (intermediate frequency) part 122. The buffer write controller 114 writes an output of the descrambler and error detector 112 into the second memory 30 under the control of the track buffer memory controller 120. The buffer read controller 118 reads out the data written in the second memory 30 and transfers it to an I/F part 126 including an audio/video decoder I/F part and a DVD-ROM I/F, under the control of the track buffer memory controller 120. The microcomputer I/F part 122 interfaces between the system decoder 18 and the microcomputer 24.
A data processing operation of the conventional system decoder 18 includes the steps of receiving the data stream ESM to detect the synchronization and ID (identification) data therefrom, and performing a data demodulation; performing an error detection and correction; and performing a descrambling and error detection for the corrected demodulation data and performing track buffering. In the track buffering operation, the track buffer memory controller 120 generates the acknowledge signal according to a predetermined priority order in response to the memory access request signal generated from the elements 114, 118, and 122, as shown in FIG. 2. Any one of the elements 114, 118 and 122, which has received the acknowledge signal generated from the track buffer memory controller 120, reads or writes the predetermined number of words from/into the second memory 30 for a predetermined time. The main data MD and error information supplied from the descrambler and error detector 112 are written by a word unit (a read/write time for one word is commonly 92 ns). Therefore, if the memory access request signal is simultaneously generated from another element, the element can not normally access the second memory 30, thereby resulting in a delay of the data transmission to the exterior of the system decoder 18.